2020 Campus—Digital IP Verification Engineer
Job Title:2020 Campus-Digital IP Verification Engineer
Location: Shanghai
Responsibility:
- This position is for leading edge IP verification
- Study existing UVM test environment and make improvements
- Define verification spec based on standard specifications
- Write and debug test cases to verify RTL design at IP level
- Collect and improve code and functional coverage
- Maintain regression tests and debug test failures
- Work with VIP teams for VIP issues
Qualification:
- Be familiar with SystemVerilog, knowledge in UVM is a plus
- Be fluent in English, both speaking and writing
- Knowledge in software programming, e.g. C/C++, Python, is a plus
- Knowledge in any high performance interface technologies, e.g. DDR, PCIe, ethernet, is a plus
- Knowledge in any chip infrastructure, e.g. RISC, AMBA protocols, is a plus
- Has strong desire to learn and explore new technologies
- Demonstrates good attitude in team work