Design for Test (DFT) Engineer - Fall Internship
Facebook Reality Labs focuses on delivering Facebook's vision through Augmented Reality (AR). Compute power requirements of Augmented Reality require custom silicon. Facebook Silicon team is driving the state of the art forward with breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable AR devices where our real and virtual world will mix and match throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistor, through architecture, to firmware, and algorithms.
Design for Test (DFT) Engineer Intern Responsibilities
- Develop and automate DFT flows
- Perform DFT rule checks using commercial DFT tools and work with designers to resolve issues
- Develop simulation testbenches to verify DFT implementation
- Review IP specifications to establish required DFT features
Minimum Qualifications
- Currently has, or is in the process of obtaining, a Bachelors or Masters in Electrical and Computer Engineering, or related field
- Must obtain work authorization in country of employment at the time of hire, and maintain ongoing work authorization during employment
- Knowledge of digital design fundamentals and computer architecture
- Experience with Python, Perl, TCL or equivalent shell scripting language
- Familiarity with SoC/ASIC design flow
Preferred Qualifications
- Intent to return to degree-program after the completion of the internship/co-op
- Knowledge of SOC design flow and DFT practices is a plus, e.g., At-Speed Test, Built-in Self-Test (BIST), Automated Test Pattern Generation (ATPG)
- Experience writing Verilog RTL and developing simulation testbenches
- Experience with commercial EDA tools for synthesis, simulation, DFT and ATPG
- Knowledge of industry test standards (IEEE1149.1, IEEE1500)